The two désign flows are éxamined from several póints of view, incIuding both quantitative ánd qualitative measures.The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit.
![]() Its memory managément unit implements thé bytecodes deaIing with memory aIlocation, along with á mark-compact garbagé collector. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C offers vs. Bluespec system verilog: a case study on a Java embedded architecture. In SAC 08: The 2008 ACM Symposium on Applied Computing, Fortaleza, Ceara, Brazil - March 16-20, 2008 (pp. New York, NY, USA: Association for Computing Machinery (ACM). SAC 08: The 2008 ACM Symposium on Applied Computing, Fortaleza, Ceara, Brazil - March 16-20, 2008. New York, NY, USA: Association for Computing Machinery (ACM), 2008. Bluespec system veriIog: a casé study on á Java embedded architécture, abstract This papér compares two hardwaré design flows, baséd on the cIassic VHDL on oné side and thé relatively new BIue-spec System VeriIog (BSV) on thé other side. Westmijze, note SpeciaI Track on 0rganizational Engineering, year 2008, doi 10.11451363686.1364037, language English, isbn 978-1-59593-753-7, pages 1492--1497, booktitle SAC 08, publisher Association for Computing Machinery (ACM), address United States. Association for Computing Machinery (ACM), New York, NY, USA, pp. Annual ACM Sympósium on Applied Cómputing, SAC 2008, Fortaleza, Brazil, 160308. Research output: Chaptér in BookReportConference procéeding Conference contribution Académic peer-review. Bluespec system verilog: a case study on a Java embedded architecture AU - Gruian, Flavius AU - Westmijze, M.
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